Deploying a neural network on an embedded solution requires more than compiling a trained model. Join us to discuss the IP and tooling available from Cadence that allow architects to start with a neural network model, run through quantization and partitioning mapping to a configurable embedded target, simulating the design to get performance data (both cycle and energy), and iterating through design optimizations to reach an optimal implementation. Our experts will give a technical walkthrough of the tools, features, supported frameworks, and infrastructure available to both software and silicon designers.
Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.
Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.
Ade Bamidele
Ade is an Architect in the Tensilica Central Applications Team. Ade focuses on the optimization and acceleration of imaging and vision algorithms on Vision and AI DSP and engines. He has over 15 years of experience in the R&D and optimization of computer vision and pattern recognition algorithms on vision and embedded devices. Ade graduated from University College London in 2006 with a Doctoral in Electronics Engineering and Thesis focusing on Computational Visual Attention.
Michael Hubrig
Michael is Sr. Architect in the Tensilica Central Applications Team. His team provides deep technical support for Vision and AI DSP and engines. Michael has 20 years of experience porting imaging and vision algorithms to DSP platforms.
Rohan Darole
Rohan Darole is a ML Product Specialist at Cadence TIP (Tensilica IP Group). He received his Master’s in Computer Science from SUNY-UB, Buffalo, NY. Rohan is leading a team of application engineers responsible for definition, realization, and customer engagements of Tensilica AI MAX Product Family. Previously he has worked on CV/ML Acceleration with Vision DSPs, Imaging (ISP) & Video Codecs SW Development.